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rev. 1.0 november 2013 www.aosmd.com page 1 of 14 AOZ3024PI ezbuck? 3 a synchronous buck regulator general description the AOZ3024PI is a high efficiency, easy to use, 3 a synchronous buck regulator. the AOZ3024PI works from 4.5 v to 18 v input voltage range, and provides up to 3 a of continuous output current with an output voltage adjustable down to 0.8 v. the AOZ3024PI comes in an exposed pad so-8 package and is rated over a -40 c to +85 c operating ambient temperature range. features ? 4.5 v to 18 v operating input voltage range ? synchronous buck: 70 m ? internal high-side switch and 40 m ? internal low-side switch (at 12 v) ? up to 95 % efficiency ? external soft start ? output voltage adjustable to 0.8 v ? 3 a continuous output current ? 500 khz pwm operation ? cycle-by-cycle current limit ? pre-bias start-up ? short-circuit protection ? thermal shutdown ? exposed pad so-8 package applications ? point-of-load dc/dc converters ? lcd tv ? set-top boxes ? dvd and blu-ray players/recorders ? cable modems typical application figure 1. 3.3 v, 3 a synchronous buck regulator, fs = 500 khz lx vin vin vout fb pgnd en comp agnd c2, c3 22f r1 r2 c c r c c1 10f l1 4.7h AOZ3024PI pgood r3 5v
AOZ3024PI rev. 1.0 november 2013 www.aosmd.com page 2 of 14 ordering information aos green products use reduced levels of halogens, and are also rohs compliant. please visit www.aosmd.com/media/aosgreenpolicy.pdf for additional information. pin configuration pin description part number ambient temperature range package environmental AOZ3024PI -40 c to +85 c epad so-8 green product 1 2 3 4 pgnd vin a gnd fb exposed pad so-8 (top view) pad (lx) lx pgood en comp 8 7 6 5 pin number pin name pin function 1 pgnd power ground. pgnd needs to be electrically connected to agnd. 2 vin supply voltage input. when vin rises above the uvlo threshold and en is logic high, the device starts up. 3 agnd analog ground. agnd is the reference point for controller section. agnd needs to be electrically connected to pgnd. 4 fb feedback input. the fb pin is used to set t he output voltage via a resistive voltage divider between the output and agnd. 5 comp external loop compensation pin. conne ct a rc network between comp and agnd to compensate the control loop. 6 en enable pin. pull en to logic high to enable the device. pull en to logic low to disable the device. if on/off control in not needed, connect en to vin and do not leave it open. 7 pgood power good output. pgood is an open-drain output that indicates the status of output voltage. 8 lx (sense) no connect pin. pin 8 is not internally connected. connect this pin externally to lx and use it for better thermal performance. exposed pad lx switching node. lx is t he drain of the internal pfet. lx is used as the thermal pad of the power stage.
AOZ3024PI rev. 1.0 november 2013 www.aosmd.com page 3 of 14 block diagram absolute maximum ratings exceeding the absolute maximum ratings may damage the device. note: 1. devices are inherently esd s ensitive, handling precautions are required. human body model rating: 1.5 k ? in series with 100 pf. recommended operating conditions the device is not guaranteed to operate beyond the maximum recommended operating conditions. 500khz oscillator agnd pgnd vin en fb comp pgood lx otp internal +5v ilimit pwm control logic 5v ldo regulator uvlo & por softstart reference & bias 0.8v q1 q2 pwm comp level shifter + fet driver isen eamp + ? + ? frequency foldback comparator + ? + ? + 0.2v over-voltage protection comparator + ? 0.96v + ? 0.72v parameter rating supply voltage (v in )20 v lx to agnd -0.7 v to v in +0.3 v lx to agnd (20 ns) -5 v to 22 v en to agnd -0.3 v to v in +0.3 v fb, pgood, comp to agnd -0.3 v to 6.0 v pgnd to agnd -0.3 v to +0.3 v junction temperature (t j ) +150 c storage temperature (t s ) -65 c to +150 c esd rating (1) 2.0 kv parameter rating supply voltage (v in ) 4.5 v to 18 v output voltage range 0.8 v to 0.85 * v in ambient temperature (t a ) -40 c to +85 c package therma l resistance exposed pad so-8 ( ? ja ) 50 c/w
AOZ3024PI rev. 1.0 november 2013 www.aosmd.com page 4 of 14 electrical characteristics t a = 25 c, v in = v en = 12 v, v out = 3.3 v unless otherwise specified. (2 ) note: 2. specification in bold indicate an ambient temperature range of -40 c to +85 c. these specificati ons are guaranteed by design. symbol parameter conditions min. typ. max. units v in supply voltage 4.5 18 v v uvlo input under-voltage lockout threshold v in rising v in falling 4.1 3.7 v i in supply current (quiescent) i out = 0, vfb = 1.2 v, v en > 2 v 1.6 2.5 ma i off shutdown supply current v en = 0 v 110 a v fb feedback voltage t a = 25 c 0.788 0.8 0.812 v load regulation 0.5 % line regulation 1% i fb feedback voltage input current 200 na v en en input threshold off threshold on threshold 2 0.6 v v hys en input hysteresis 200 mv en leakage current 1 a ss time 34.56 ms modulator f o frequency 400 500 600 khz d max maximum duty cycle 85 % t min controllable minimum on time 150 ns current sense transconductance 8 a / v error amplifier transconductance 200 a / v protection i lim current limit 3.5 4.5 a v ovp over-voltage protection off threshold on threshold 960 800 mv over-temperature shutdown limit t j rising t j falling 150 100 c power good v olpg pg low voltage i ol = 1ma 0.25 v pg leakage 1a v pgl pg threshold voltage (rising) 88 91 93 % / v pg threshold hysteresis 3 % t pg pg delay time 128 s output stage high-side switch on-resistance v in = 12 v v in = 5 v 70 110 m ? low-side switch on-resistance v in = 12 v v in = 5 v 40 50 m ?
rev. 1.0 november 2013 www.aosmd.com page 5 of 14 AOZ3024PI typical performance characteristics circuit of figure 1. t a = 25 c, v in = v en = 12 v, v out = 3.3 v unless otherwise specified. light load operation 2s/div start up to full load 5ms/div full load operation 2s/div short circuit protection 20ms/div short circuit recovery 20ms/div vin ripple 0.5v/div vo ripple 50mv/div vlx 10v/div il 2a/div vin 5v/div vo 2v/div vo 2v/div vlx 10v/div il 2a/div vo 2v/div vlx 10v/div il 2a/div 50% to 100% load transient 100s/div vo ripple 0.2v/div io 2a/div vin ripple 0.2v/div vo ripple 50mv/div vlx 10v/div il 2a/div
AOZ3024PI rev. 1.0 november 2013 www.aosmd.com page 6 of 14 efficiency detailed description the AOZ3024PI is a current-mode step down regulator with an integrated high-side pmos switch and a low-side nmos switch. the AOZ3024PI operates from a 4.5 v to 18 v input voltage range and supplies up to 3 a of load current. features include enable control, power-on reset, input under voltage lockout, output over voltage protection, external soft-start and thermal shut down. the AOZ3024PI is available in an exposed pad so-8 package. enable and soft start the AOZ3024PI has an internal soft start feature to limit in-rush current and ensure the output voltage ramps up smoothly to regulation voltage. the soft start process begins when the input voltage rises to 4.1 v and voltage on the en pin is high. in the soft start process, the output voltage is typically ramped to regulation voltage in 4.5ms. the 4.5ms soft start time is set internally. the en pin of the AOZ3024PI is active high. connect the en pin to vin if the enable function is not used. pulling en to ground will disable th e AOZ3024PI. do not leave en open. the voltage on the en pin must be above 2 v to enable the AOZ3024PI. when the en pin voltage falls below 0.6 v, the AOZ3024PI is disabled. power good the power good output is an open drain n-channel mosfet which supplies an active-high power good stage. a pull-up resistor should connect this pin to a dc power trail with maximum voltage of 6 v. the AOZ3024PI also monitors the fb voltage. when the fb voltage is lower than 90 % of the normal voltage, the n-channel mosfet turns on and the power good pin is pulled low, this indicates the power is abnormal. steady-state operation under heavy load steady-state conditions, the converter operates in fixed frequency and continuous-conduction mode (ccm). the AOZ3024PI integrates an internal p-mosfet as the high-side switch. inductor curren t is sensed by amplifying the voltage drop across the drain to source of the high side power mosfet. output voltage is divided down by the external voltage divider at the fb pin. the difference of the fb pin voltage and reference voltage is amplified by the internal transconductance error amplifier. the error voltage, which shows on the comp pin, is compared against the current signal, which is the sum of inductor current signal and ramp compensation signal, at the pwm comparator input. if the current signal is less than the error voltage, the inte rnal high-side switch is on. efficiency (v in = 12v, l = 4.7h) vs. load current 100 95 90 85 80 75 70 65 60 55 50 0 0.5 1.0 1.5 2.0 2.5 3.0 load current (a) efficiency (%) 5v output 3.3v output 1.8v output 1.2v output
AOZ3024PI rev. 1.0 november 2013 www.aosmd.com page 7 of 14 the inductor current flows from the input through the inductor to the output. when the current si gnal exceeds the error voltage, the high-side switch is off. the inductor current is freewheeling through the internal low-side n-mosfet switch to output. the internal adaptive fet driver guarantees no turn on overlap of both the high-side and the low-side switch. compared with regulators using freewheeling schottky diodes, the AOZ3024PI uses a freewheeling nmosfet to realize synchronous rect ification. this greatly improves the converter efficiency and reduces power loss in the low-side switch. the AOZ3024PI uses a p-channel mosfet as the high-side switch. this saves the bootstrap capacitor normally seen in a circuit using an nmos switch. output voltage programming output voltage can be set by feeding back the output to the fb pin using a resistor divider network as shown in figure 1. the resistor divider network includes r 1 and r 2 . usually, a design is started by picking a fixed r 2 value and calculating the required r 1 with the equation below: some standard value of r 1 and r 2 for the most common output voltages are listed in table 1. table 1. the combination of r 1 and r 2 should be large enough to avoid drawing excessive current from the output, which will cause power loss. protection features the AOZ3024PI has multiple protection features to prevent system circuit damage under abnormal conditions. over current protection (ocp) the sensed inductor current signal is also used for over current protection. since the AOZ3024PI employs peak current mode control, the comp pin voltage is proportional to the peak indu ctor current. the comp pin voltage is limited to be between 0.4 v and 2.5 v internally. the peak inductor current is automatically limited cycle-by-cycle. when the output is shorted to ground under fault conditions, the inductor current slowly decays during a switching cycle because the output voltage is 0 v. to prevent catastrophic failure, AOZ3024PI detects the duration when the over-current condition occurs. if the over- current condition occurs for a certain period of time, AOZ3024PI completely turn s off momentarily, then restarts. if the fault is still present, then the device will turn off again. the converter will initiate a soft start once the over-current condition disappears. power-on reset (por) a power-on reset circuit monitors the input voltage. when the input voltage exceeds 4. 1 v, the converter starts operation. when input voltage falls below 3.7 v, the converter will be shut down. thermal protection an internal temperature sensor monitors the junction temperature. the sensor shuts down the internal control circuit and high side pmos if the junction temperature exceeds 150 oc. the regulato r will restart automatically under the control of the soft-start circuit when the junction temperature decreases to 100 oc. v o (v) r 1 (k ? ) r 2 (k ? ) 0.8 1.0 open 1.2 4.99 10 1.5 10 11.5 1.8 12.7 10.2 2.5 21.5 10 3.3 31.1 10 5.0 52.3 10 v o 0.8 1 r 1 r 2 ------ - + ?? ?? ?? ? =
AOZ3024PI rev. 1.0 november 2013 www.aosmd.com page 8 of 14 application information the basic AOZ3024PI application circuit is show in figure 1. component selection is explained below. input capacitor the input capacitor must be connected to the v in pin and the pgnd pin of AOZ3024PI to maintain steady input voltage and filter out the pulsing input current. the voltage rating of input capacitor must be greater than maximum input voltage plus ripple voltage. the input ripple voltage can be approximated by equation below: since the input current is discontinuous in a buck converter, the current stress on the input capacitor is another concern when selecting the capacitor. for a buck circuit, the rms value of input capacitor current can be calculated by: if we let m equal the conversion ratio: the relationship between the input capacitor rms current and voltage conversion ratio is calculated and shown in figure 2 below. it can be seen that when v o is half of v in , c in is under the worst current stress. the worst current stress on c in is 0.5 x i o . figure 2. i cin vs. voltage conversion ratio for reliable operation and best performance, the input capacitors must have a cu rrent rating higher than i cin_rms at the worst operating conditions. ceramic capacitors are preferred for input capacitors because of their low esr and high current rating. depending on the application circuits, other low esr tantalum capacitors may be used. when selecting ceramic capacitors, x5r or x7r type dielectric ceramic capacitors should be used for their better temperature and voltage characteristics. note that the ripple curr ent rating from capacitor manufactures are based on a certain operating life time. further de-rating may need to be considered for long term reliability. inductor the inductor is used to supply constant current to output when it is driven by a switching voltage. for a given input and output voltage, inductance and switching frequency together decide the inductor ripple current, which is: the peak inductor current is: high inductance gives low inductor ripple current but requires larger size inductor to avoid saturation. low ripple current reduces induct or core losses. it also reduces rms current through inductor and switches, which results in less conduction loss. usually, peak to peak ripple current on the inductor is designed to be 20 % to 40 % of output current. when selecting the inductor, confirm it is able to handle the peak current without saturation at the highest operating temperature. the inductor takes the highest current in a buck circuit. the conduction loss on the inductor needs to be checked for thermal and efficiency requirements. surface mount inductors in different shape and styles are available from coilcraft, elytone and murata. shielded inductors are small and radiate less emi noise. however, they cost more than unshie lded inductors. the choice depends on emi requirement, price and size. ? v in i o fc in ? ----------------- 1 v o v in -------- - ? ?? ?? ?? v o v in -------- - ? ? = i cin_rms i o v o v in -------- - 1 v o v in -------- - ? ?? ?? ?? ? = v o v in -------- - m = 0 0.1 0.2 0.3 0.4 0.5 0 0.5 1 m i cin_rms (m) i o ? i l v o fl ? ---------- - 1 v o v in -------- - ? ?? ?? ?? ? = i lpeak i o ? i l 2 -------- + =
AOZ3024PI rev. 1.0 november 2013 www.aosmd.com page 9 of 14 output capacitor the output capacitor is selected based on the dc output voltage rating, output ripple voltage specification and ripple current rating. the selected output capacito r must have a higher rated voltage specification than the maximum desired output voltage including ripple. de-rating needs to be considered for long term reliability. output ripple voltage specification is another important factor for selecting the output capacitor. in a buck converter circuit, output ripple voltage is determined by inductor value, switching fr equency, output capacitor value and esr. it can be calculated by the equation below: where, c o is output capacitor value, and esr co is the equivalent series resistance of the output capacitor. when a low esr ceramic capacitor is used as the output capacitor, the impedance of the capacitor at the switching frequency dominates. output ripple is mainly caused by capacitor value and inductor ripple current. the output ripple voltage calculation can be simplified to: if the impedance of esr at switching frequency dominates, the output ripple vo ltage is mainly decided by capacitor esr and inductor ripple current. the output ripple voltage calculation can be further simplified to: for lower output ripple voltage across the entire operating temperature range, x5r or x7r dielectric type of ceramic, or other low esr tantalum capacitors are recommended as output capacitors. in a buck converter, out put capacitor current is continuous. the rms current of output capacitor is decided by the peak to peak inductor ripple current. it can be calculated by: usually, the ripple current rating of the output capacitor is a smaller issue because of the low current stress. when the buck inductor is selected to be very small and inductor ripple current is hi gh, the output capacitor could be overstressed. loop compensation the AOZ3024PI employs peak current mode control for ease of use and fast transient response. peak current mode control eliminates the double pole effect of the output l&c filter. it also greatly simplifies the compensation loop design. with peak current mode control, the buck power stage can be simplified to be a one-pole and one-zero system in frequency domain. the pole is dominant pole can be calculated by: the zero is a esr zero due to the output capacitor and its esr. it is can be calculated by: where; c o is the output filter capacitor, r l is load resistor value, and esr co is the equivalent series resistance of output capacitor. the compensation design shapes the converter control loop transfer function for the desired gain and phase. several different types of compensation networks can be used with the AOZ3024PI. for most cases, a series capacitor and resistor network connected to the comp pin sets the pole-zero and is adequate for a stable high-bandwidth control loop. in the AOZ3024PI, fb and comp are the inverting input and the output of the internal error amplifier. a series r and c compensation network connected to comp provides one pole and one zero. the pole is: where; g ea is the error amplifier transconductance, which is 200 x 10 -6 a/v, g vea is the error amplifier voltage gain, which is 500 v/v, and c c is the compensation capacitor in figure 1. ? v o ? i l esr co 1 8 fc o ? ? ------------------------- + ?? ?? ? = ? v o ? i l 1 8 fc o ? ? ------------------------- ? = ? v o ? i l esr co ? = i co_rms ? i l 12 ---------- = f p 1 1 2 ? c o r l ? ? ---------------------------------- - = f z 1 1 2 ? c o esr co ? ? ------------------------------------------------ = f p 2 g ea 2 ? c c g vea ? ? ------------------------------------------ - =
AOZ3024PI rev. 1.0 november 2013 www.aosmd.com page 10 of 14 the zero given by the external compensation network, capacitor c c and resistor r c , is located at: to design the compensation circuit, a target crossover frequency f c to close the loop must be selected. the system crossover frequency is where the control loop has unity gain. the crossover is the also called the converter bandwidth. generally a higher bandwidth means faster response to lo ad transients. however, the bandwidth should not be too high because of system stability concern. when de signing the compensation loop, converter stab ility under all line an d load condition must be considered. usually, it is recommended to set the bandwidth to be equal or less than 1/10 of the switching frequency. the strategy for choosing r c and c c is to set the cross over frequency with r c and set the compensator zero with c c . using selected cr ossover frequency, f c , to calculate r c : where; f c is the desired crossover frequency. for best performance, f c is set to be about 1/10 of the switching frequency; v fb is 0.8v, g ea is the error amplifier transconductance, which is 200 x 10 -6 a/v, and g cs is the current sense circui t transconductance, which is 8 a/v the compensation capacitor c c and resistor r c together make a zero. this zero is put somewhere close to the dominate pole f p1 but lower than 1/5 of the selected crossover frequency. c c can is selected by: the above equation can be simplified to: an easy-to-use application software which helps to design and simulate the compensation loop can be found at www.aosmd.com . thermal management and layout considerations in the AOZ3024PI buck regulator circuit, high pulsing current flows through two circuit loops. the first loop starts from the input capacito rs, to the vin pin, to the lx pad, to the filter induct or, to the output capacitor and load, and then returns to the input capacitor through ground. current flows in the first loop when the high side switch is on. the second loop starts from the inductor, to the output capacitors and load, to the low side nmosfet. current flows in the second loop when the low side nmosfet is on. in pcb layout, minimizing the area of the two loops will reduce the noise of the circuit and improves efficiency. a ground plane is strongly recommended to connect the input capacitor, the output capacitor, and the pgnd pin of the AOZ3024PI. in the AOZ3024PI buck regula tor circuit, the major power dissipating components are the AOZ3024PI and the output inductor. the total power dissipation of converter circuit can be measured by input power minus output power: the power dissipation of the inductor can be approximately calculated by the output current and dcr value of the inductor: the actual junction temperature can be calculated by the power dissipation in the AOZ3024PI and the thermal impedance from junction to ambient: the maximum junction temperature of the AOZ3024PI is 150 oc, which limits the maximu m load current capability. please see the thermal de-rating curves for maximum load current of the AOZ3024PI under different ambient temperatures. the thermal performance of the AOZ3024PI is strongly affected by the pcb layout. care should be taken during the design process to ensure that the ic will operate under the recommended environmental conditions. f z 2 1 2 ? c c r c ? ? ----------------------------------- = r c f c v o v fb ---------- 2 ? c c ? g ea g cs ? ----------------------------- - ? ? = c c 1.5 2 ? r c f p 1 ? ? ----------------------------------- = c c c o r l ? r c --------------------- = p total_loss v in i in v o i o ? ? ? = p inductor_loss i o 2 r inductor 1.1 ? ? = t junction p total_loss p inductor_loss ? ??? ? ja =
AOZ3024PI rev. 1.0 november 2013 www.aosmd.com page 11 of 14 layout considerations the AOZ3024PI is an exposed pad so-8 package. several layout tips are listed for the best electric and thermal performance. 1. the exposed pad (lx) is connected to the internal pfet and nfet drains. connected a large copper plane to the lx pin to help thermal dissipation. 2. do not use a thermal relief connection to the vin pin or the pgnd pin. pour a maximized copper area to the pgnd pin and the vin pin to help thermal dissipation. 3. the input capacitor should be connected as close as possible to the vin pin and the pgnd pin. 4. a ground plane is preferred. if a ground plane is not used, separate pgnd from agnd and only connect them at one point to avoid the pgnd pin noise coupling to the agnd pin. 5. make the current trace from the lx pad to l to co to the pgnd as short as possible. 6. pour copper plane on all unused board area and connect it to stable dc nodes, like vin, gnd or vout. 7. keep sensitive signal trace away from the lx pad.
AOZ3024PI rev. 1.0 november 2013 www.aosmd.com page 12 of 14 package dimensions, so-8 ep1 notes: 1. package body sizes exclude mold flash and gate burrs. 2. dimension l is measured in gauge plane. 3. tolerance 0.10mm unless otherwise specified. 4. controlling dimension is millimeter, converted inch dimensions are not necessarily exact. 5. die pad exposure size is according to lead frame design. 6. followed from jedec ms-012 symbols a a1 a2 b c d d0 d1 e e e1 e2 e3 l y | l1?l1' | l1 dimensions in millimeters recommended land pattern min. 1.40 0.00 1.40 0.31 0.17 4.80 3.20 3.10 5.80 ? 3.80 2.21 0.40 ? 0 ? d0 unit: mm nom. 1.55 0.05 1.50 0.406 ? 4.96 3.40 3.30 6.00 1.27 3.90 2.41 0.40 ref 0.95 ? 3 0.04 1.04 ref max. 1.70 0.10 1.60 0.51 0.25 5.00 3.60 3.50 6.20 ? 4.00 2.61 1.27 0.10 8 0.12 dimensions in inches d1 e1 e e3 e2 note 5 l1' l1 l gauge plane 0.2500 c d 7 (4x) b 3.70 2.20 2.87 2.71 5.74 1.27 0.80 0.635 e a1 a2 a symbols a a1 a2 b c d d0 d1 e e e1 e2 e3 l y | l1?l1' | l1 min. 0.055 0.000 0.055 0.012 0.007 0.189 0.126 0.122 0.228 ? 0.150 0.087 0.016 ? 0 ? nom. 0.061 0.002 0.059 0.016 ? 0.195 0.134 0.130 0.236 0.050 0.153 0.095 0.016 ref 0.037 ? 3 0.002 0.041 ref max. 0.067 0.004 0.063 0.020 0.010 0.197 0.142 0.138 0.244 ? 0.157 0.103 0.050 0.004 8 0.005
AOZ3024PI rev. 1.0 november 2013 www.aosmd.com page 13 of 14 tape and reel dimensions, so-8 ep1 carrier tape reel tape size 12mm reel size ?330 m ?330.00 0.50 package so-8 (12mm) a0 6.40 0.10 b0 5.20 0.10 k0 2.10 0.10 d0 1.60 0.10 d1 1.50 0.10 e 12.00 0.10 e1 1.75 0.10 e2 5.50 0.10 p0 8.00 0.10 p1 4.00 0.10 p2 2.00 0.10 t 0.25 0.10 n ?97.00 0.10 k0 unit: mm b0 g m w1 s k h n w v r trailer tape 300mm min. or 75 empty pockets components tape orientation in pocket leader tape 500mm min. or 125 empty pockets a0 p1 p2 feeding direction p0 e2 e1 e d0 t d1 w 13.00 0.30 w1 17.40 1.00 h ?13.00 +0.50/-0.20 k 10.60 s 2.00 0.50 g ? r ? v ? leader/trailer and orientation unit: mm
AOZ3024PI rev. 1.0 november 2013 www.aosmd.com page 14 of 14 part marking z3024pi fay part number code assembly lot code year & week code wlt fab & assembly location as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. legal disclaimer alpha and omega semiconductor makes no representations or warranties with respect to the accuracy or completeness of the information provid ed herein and takes no liabilities fo r the consequences of use of such information or any product described herein. alpha and omega semiconductor reserves the right to make changes to such information at any time without furt her notice. this document does not co nstitute the grant of any intellectual property rights or representation of non-infringement of any third party?s intellectual property rights. life support policy alpha & omega semiconductor products are not author ized for use as critical components in life support devices or systems.

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